1. Field of the Invention
The present invention relates generally to electronic circuits, and more specifically to a system and method for obtaining frame synchronization by a receiver within a serial bit stream.
2. Description of the Prior Art
High speed serial data links are usually used when it is desired to transmit data over long distances. Typically, parallel data is serialized, transmitted as a serial bit stream, and reassembled into the original parallel information at the receiving end. The transmitted data can represent actual digital information, or may represent analog information which has been sampled and digitized.
When transmitting serial data, it is important that the sender and receiver be kept in synchronization. This can be done in many ways, one of which is the inclusion of synchronization information in the data stream. Such synchronization information is placed into the data stream by the transmitting device, and removed therefrom by the receiving device. The synchronization information comprises one or more special codes which are looked for by the receiving device. The synchronization codes can be located together, such as in a frame header, or may be distributed as individual bits within the data.
An example of the latter approach is found in the T1 standard promulgated by AT&T, and used for multiplexed telephone transmissions. In the T1 standard, 24 8-bit data channels are grouped together into a serial data packet called a frame. Each frame also contains one framing bit, which is the first bit of the frame. This gives a total of 193 bits for each frame. Frames are transmitted at a rate of 8192 frames per second, which is the standard data transmission rate for CODECs used to digitize and restore voice and other analog signals.
A single data frame is shown in FIG. 1. The first bit to be transmitted, bit 0, is the frame bit. The remaining 192 bits of the frame contain 24 channels of 8-bit data as shown. The frame bit F is inserted into the data stream by the transmitting device, and removed by the receiving device after it is used for synchronization purposes.
According to the T1 standard, frames are grouped into sets called multiframes, or super frames. The 193s standard uses 12 frames in a multiframe, and the 193e standard uses 24 frames in a multiframe. An example of a 193e multiframe is shown in FIG. 2. 24 consecutively transmitted frames are defined to be a multiframe. The frame bits from each of the 24 frames are used in combination to identify which frame is frame 1 of the multiframe, and for other purposes.
At the receiving device, synchronization of the incoming serial data stream is performed by examining the stream, and identifying which bits are the frame bits. There is no additional information to identify these bits; they must be extracted out of the data by looking for preselected patterns used by the framing bits. The pattern of frame bits within a multiframe is used to identify the frame bits, thereby defining data frames, and for determining the boundaries of each multiframe.
As an example, using the 193e standard, the frame bits for frame numbers 4, 8, 12, 16, 20, and 24 are assigned the pattern 001011. The frame bits for the odd numbered frames form a low bandwidth data channel which can be used for control and signaling purposes. The frame bits for frames 2, 6, 10, 14, 18, and 22, taken together, define a CRC word for the previously transmitted multiframe.
Because the data transmitted on the serial channel is essentially random for synchronization purposes, the receiver cannot immediately extract the position of the framing bits and multiframes from the data stream. The receiver must examine the incoming data stream for some period of time in order to determine frame alignment, which is defined by the location of the frame bits. Once the frame bits are properly located, the multiframe alignment is determined by looking for the position of the 001011 pattern described above.
Examples of prior art circuits for establishing frame and multiframe alignment are found in U.S. Pat. No. 4,727,558, issued to Hall, and U.S. Pat. No. 4,316,284, issued to Howson. The systems described in these patents both use the same technique for establishing frame and multiframe alignment. A large shift register is used to store a portion of the received serial data stream. The shift register is tapped at 4 points which are 772 bits apart (4 frames apart), and the systems look for the 4-bit subsequences which are obtainable from the repeating 001011 pattern. A 772 bit shift register is used to hold candidate positions for frame bit positions. This shift register is shifted synchronously with data entering the large shift register. As invalid multiframe patterns are observed at the tap locations, the corresponding position out of 772 is marked in the 772 bit shift register as no longer being a valid candidate position.
A counter is connected to the 772 bit shift register for counting how many candidate positions remain. Each time the 772 bit shift register is shifted through one complete cycle, the counter determines whether 0, 1, or more than 1 candidate positions currently remain. Eventually, the 772 bit shift register contains exactly 1 remaining candidate position, which is taken to be the true location of the framing bits for frames 4, 8, 12, 16, 20, and 24. Multiframe alignment by matching the values of the bits corresponding to the position identified in the 772 shift register with the 001011 pattern is then straightforward.
It would be desirable to provide a synchronization circuit for a serial data receiver which has improved response, and which is simply and easily designed into a portion of an integrated circuit.